This invention relates to a serial input/output memory, and more particularly, to a device for increasing transmission speed of test bits in a test operation in the serial input/output memory using a serial clock applied from an exterior source as an internal clock, by converting a frequency of the serial clock.
Generally, it is well known that a serial transmission method is useful in transmission between a system such as a central processing unit for processing data in parallel and a system such as an auxiliary unit for processing data in series. A transmitter sends each bit of the data separately and a receiver assembles the bits in order to reconstruct the data upon reception. For example, the receiver completes a word after receiving eight bits sequentially, in the case where one word comprises eight bits.
An universal asynchronous receiver and transmitter (hereinafter referred to as "UART") is widely used as such an interface device. A transmission method using the UART is called an UART protocol method.
In the UART protocol method, input data is transmitted to a memory core through a plurality of shift registers; and likewise output data is transmitted through a plurality of shift registers to an external side of an accessed memory, to be received as data bits in serial format (hereinafter referred to as a "serial block memory"). Such shift registers for transmitting data are controlled by an internal clock at various frequencies based on a serial clock (called a "system clock.sub.XSX ").
In conventional serial input and output memory devices, test time is delayed unnecessarily because the internal control clock (which has a frequency that is 1/512 times the system clock) is passed through nine counters prior to use in testing character and access functions of a chip.